`timescale 1ns/1ns

module mux(
           input clk_a,
           input clk_b,
           input arstn,
           input brstn,
           input [3: 0] data_in,
           input data_en,

           output reg [3: 0] dataout
       );

reg data_en_a;
reg [3: 0] data_in_a;

always@(posedge clk_a or negedge arstn)
	begin
		if (!arstn)
			begin
				data_en_a <= 0;
				data_in_a <= 4'd0;
			end
		else
			begin
				data_en_a <= data_en;
				data_in_a <= data_in;
			end
	end

reg data_en_a_r, data_en_a_b;
always@(posedge clk_b or negedge brstn)
	begin
		if (!brstn)
			{data_en_a_b, data_en_a_r} <= {1'b0, 1'b0};
		else
			{data_en_a_b, data_en_a_r} <= {data_en_a_r, data_en_a};
	end

always@(posedge clk_b or negedge brstn)
	begin
		if (!brstn)
			begin
				dataout <= 4'b0 ;
			end
		else if (data_en_a_b)
			begin
				dataout <= data_in_a;
			end
		else
			dataout <= dataout;
	end

endmodule
